Variable Mapping of System Level Design

This report presents a variable-memory mapping approach of the system level design, which maps the variables of the system behavior to the memories of the system architecture. It first introduces a novel memory size model to compute the required minimal memory sizes when allowing variables with un-overlapped lifetime to share the same memory portion. It then presents variable mapping algorithms for different design assumptions. The variable mapping algorithms are applied before obtaining some implementation details, such as bus topology and bus protocols, which moves the variable mapping to the earliest design stage.